The present invention relates to power on reset in a semiconductor integrated circuit.
Japanese Unexamined Patent Publication No. 2002-111466 describes a technique of providing power on reset circuits corresponding to a plurality of external power supply and determining a timing of cancelling power on reset in an internal circuit by using an AND signal of outputs of the power on reset circuits. In the technique, the power on reset is performed to ensure an initial state of a circuit until power supply voltage reaches a specific voltage at turn-on of an operation power supply. Japanese Unexamined Patent Publication No. 2004-165732 describes an invention of generating a power on reset cancelling timing on the basis of an AND signal between detection signals of an internal voltage detecting circuit and an external voltage detecting circuit.